Pulse-Width Modulator (PWM8B6CV1) Block Description
due to the synchronization of PWMEx and the clock source. An exception to this is when channels are
concatenated. Refer to Section 10.4.2.7, “PWM 16-Bit Functions,” for more detail.
NOTE
The first PWM cycle after enabling the channel can be irregular.
On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high.
There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an
edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.
10.4.2.2 PWM Polarity
Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown
on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip-flop.
When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the
beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit
is 0, the output starts low and then goes high when the duty count is reached.
10.4.2.3 PWM Period and Duty
Dedicated period and duty registers exist for each channel and are double buffered so that if they change
while the channel is enabled, the change will NOT take effect until one of the following occurs:
•
•
•
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period and duty registers will go
directly to the latches as well as the buffer.
A change in duty or period can be forced into effect “immediately” by writing the new value to the duty
and/or period registers and then writing to the counter. This forces the counter to reset and the new duty
and/or period values to be latched. In addition, because the counter is readable it is possible to know where
the count is with respect to the duty value and software can be used to make adjustments.
NOTE
When forcing a new period or duty into effect immediately, an irregular
PWM cycle can occur.
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time.
10.4.2.4 PWM Timer Counters
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source
(reference Figure 10-34 for the available clock sources and rates). The counter compares to two registers,
a duty register and a period register as shown in Figure 10-35. When the PWM counter matches the duty
register the output flip-flop changes state causing the PWM waveform to also change state. A match
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