Freescale’s Scalable Controller Area Network (S12MSCANV3)
•
For transmit buffers, anytime when TXEx flag is set (see Section 8.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 8.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
•
Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation
Figure 8-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
IDR0
0x00X0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
W
R
IDR1
0x00X1
ID2
ID1
ID0
RTR
IDE (=0)
W
R
IDR2
0x00X2
W
R
IDR3
0x00X3
W
= Unused, always read ‘x’
8.3.3.1
Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
S12P-Family Reference Manual, Rev. 1.13
278
Freescale Semiconductor
FREESCALE [ Freescale ]
