Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 8-26. Message Buffer Organization
Offset
Address
Register
Access
0x00X0
0x00X1
0x00X2
0x00X3
0x00X4
0x00X5
0x00X6
0x00X7
0x00X8
0x00X9
0x00XA
0x00XB
0x00XC
0x00XD
0x00XE
0x00XF
Identifier Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Identifier Register 1
Identifier Register 2
Identifier Register 3
Data Segment Register 0
Data Segment Register 1
Data Segment Register 2
Data Segment Register 3
Data Segment Register 4
Data Segment Register 5
Data Segment Register 6
Data Segment Register 7
Data Length Register
Transmit Buffer Priority Register(1)
Time Stamp Register (High Byte)
Time Stamp Register (Low Byte)
R
1. Not applicable for receive buffers
Figure 8-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 8-25.
1
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation .
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
Figure 8-24. Receive/Transmit Message Buffer — Extended Identifier Mapping
Register
Name
Bit 7
6
5
4
3
2
1
Bit0
R
0x00X0
IDR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
W
R
0x00X1
IDR1
ID20
ID14
ID6
ID19
ID13
ID5
ID18
ID12
ID4
SRR (=1)
ID11
IDE (=1)
ID10
ID17
ID9
ID16
ID8
ID15
ID7
W
R
0x00X2
IDR2
W
R
0x00X3
IDR3
ID3
ID2
ID1
ID0
RTR
W
1. Exception: The transmit buffer priority registers are 0 out of reset.
S12P-Family Reference Manual, Rev. 1.13
276
Freescale Semiconductor
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