Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
Table 8-9. Time Segment 2 Values
TSEG22
TSEG21
TSEG20
Time Segment 2
0
0
:
0
0
1 Tq clock cycle(1)
2 Tq clock cycles
:
0
:
1
:
1
1
1
1
0
1
7 Tq clock cycles
8 Tq clock cycles
1. This setting is not valid. Please refer to Table 8-37 for valid settings.
Table 8-10. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
1 Tq clock cycle(1)
2 Tq clock cycles1
3 Tq clock cycles1
4 Tq clock cycles
:
1
1
1
1
1
1
0
1
15 Tq clock cycles
16 Tq clock cycles
1. This setting is not valid. Please refer to Table 8-37 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 8-9 and Table 8-10).
Eqn. 8-1
(Prescaler value)
-----------------------------------------------------
f
Bit Time=
• (1 + TimeSegment1 + TimeSegment2)
CANCLK
8.3.2.5
MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
S12P-Family Reference Manual, Rev. 1.13
262
Freescale Semiconductor
FREESCALE [ Freescale ]
