Freescale’s Scalable Controller Area Network (S12MSCANV3)
Module Base + 0x0006
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
TXE2
TXE1
TXE0
Reset:
0
0
0
0
0
1
1
1
= Unimplemented
Figure 8-10. MSCAN Transmitter Flag Register (CANTFLG)
1. Read: Anytime
Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored
NOTE
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
Table 8-13. CANTFLG Register Field Descriptions
Description
Field
2-0
TXE[2:0]
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 8.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a transmit
interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 8.3.2.10, “MSCAN Transmitter
Message Abort Acknowledge Register (CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
is cleared (see Section 8.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”).
When listen-mode is active (see Section 8.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx flags
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
8.3.2.8
MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Module Base + 0x0007
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
TXEIE2
TXEIE1
TXEIE0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
S12P-Family Reference Manual, Rev. 1.13
266
Freescale Semiconductor
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