Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 8-6. Synchronization Jump Width (continued)
SJW1
SJW0
Synchronization Jump Width
0
1
1
1
0
1
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
Table 8-7. Baud Rate Prescaler
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Prescaler value (P)
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
1
2
3
4
:
1
1
1
1
1
1
64
8.3.2.4
MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Module Base + 0x0003
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
SAMP
W
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
Reset:
0
0
0
0
0
0
0
0
Figure 8-7. MSCAN Bus Timing Register 1 (CANBTR1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 8-8. CANBTR1 Register Field Descriptions
Field
Description
7
Sampling — This bit determines the number of CAN bus samples taken per bit time.
SAMP
0 One sample per bit.
1 Three samples per bit(1)
.
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
6-4
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG2[2:0] of the sample point (see Figure 8-44). Time segment 2 (TSEG2) values are programmable as shown in Table 8-
9.
3-0
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG1[3:0] of the sample point (see Figure 8-44). Time segment 1 (TSEG1) values are programmable as shown in Table 8-
10.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
261
FREESCALE [ Freescale ]
