Freescale’s Scalable Controller Area Network (S12MSCANV3)
Register
Bit 7
6
5
4
3
2
1
Bit 0
Name
0x000E
R
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
CANRXERR
W
0x000F
R
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
CANTXERR
W
0x0010–0x0013
CANIDAR0–3
R
AC7
AM7
AC7
AM7
AC6
AM6
AC6
AM6
AC5
AM5
AC5
AM5
AC4
AM4
AC4
AM4
AC3
AM3
AC3
AM3
AC2
AM2
AC2
AM2
AC1
AM1
AC1
AM1
AC0
AM0
AC0
AM0
W
0x0014–0x0017
CANIDMRx
R
W
0x0018–0x001B
CANIDAR4–7
R
W
0x001C–0x001F
CANIDMR4–7
R
W
0x0020–0x002F
CANRXFG
R
See Section 8.3.3, “Programmer’s Model of Message Storage”
W
0x0030–0x003F
CANTXFG
R
See Section 8.3.3, “Programmer’s Model of Message Storage”
= Unimplemented or Reserved
W
Figure 8-3. MSCAN Register Summary (continued)
8.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
8.3.2.1
MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
S12P-Family Reference Manual, Rev. 1.13
256
Freescale Semiconductor
FREESCALE [ Freescale ]
