Freescale’s Scalable Controller Area Network (S12MSCANV3)
The detailed register descriptions follow in the order they appear in the register map.
Register
Name
Bit 7
RXFRM
CANE
SJW1
6
5
4
3
2
1
Bit 0
0x0000
CANCTL0
R
RXACT
SYNCH
CSWAI
LOOPB
BRP5
TIME
BORM
BRP3
WUPE
WUPM
BRP2
SLPRQ
SLPAK
INITRQ
INITAK
W
0x0001
CANCTL1
R
CLKSRC
SJW0
LISTEN
BRP4
W
0x0002
CANBTR0
R
BRP1
TSEG11
OVRIF
OVRIE
TXE1
BRP0
TSEG10
RXF
W
0x0003
CANBTR1
R
SAMP
WUPIF
TSEG22
CSCIF
TSEG21
RSTAT1
TSEG20
RSTAT0
TSEG13
TSTAT1
TSEG12
TSTAT0
W
0x0004
CANRFLG
R
W
0x0005
CANRIER
R
WUPIE
0
CSCIE
0
RSTATE1 RSTATE0
TSTATE1
0
TSTATE0
TXE2
RXFIE
TXE0
W
0x0006
CANTFLG
R
0
0
0
0
0
0
0
0
0
0
W
0x0007
CANTIER
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXEIE2
TXEIE1
TXEIE0
W
0x0008
CANTARQ
R
ABTRQ2
ABTAK2
ABTRQ1
ABTAK1
ABTRQ0
ABTAK0
W
0x0009
CANTAAK
R
W
0x000A
CANTBSEL
R
TX2
TX1
TX0
W
0x000B
CANIDAC
R
IDHIT2
IDHIT1
IDHIT0
IDAM1
0
IDAM0
0
W
0x000C
Reserved
R
0
0
0
0
0
W
0x000D
CANMISC
R
0
0
BOHOLD
W
= Unimplemented or Reserved
Figure 8-3. MSCAN Register Summary
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
255
FREESCALE [ Freescale ]
