Interrupt Module (S12SINTV1)
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2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
I bit maskable interrupts can be nested.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
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One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU
request
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Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.
4.1.3
Modes of Operation
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Run mode
This is the basic mode of operation.
Wait mode
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In wait mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from wait mode if an interrupt occurs. Please refer to Section 4.5.3, “Wake Up
from Stop or Wait Mode” for details.
Stop Mode
In stop mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from stop mode if an interrupt occurs. Please refer to Section 4.5.3, “Wake Up
from Stop or Wait Mode” for details.
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to Section 4.3.1.1, “Interrupt Vector Base Register (IVBR)” for details.
4.1.4
Block Diagram
Figure 4-1 shows a block diagram of the INT module.
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
S12P-Family Reference Manual, Rev. 1.13
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