Interrupt Module (S12SINTV1)
Peripheral
Interrupt Requests
Wake Up
CPU
Vector
Address
Non I bit Maskable Channels
I bit Maskable Channels
IVBR
Interrupt
Requests
Figure 4-1. INT Block Diagram
4.2
External Signal Description
The INT module has no external signals.
4.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
4.3.1
Register Descriptions
This section describes in address order all the INT registers and their individual bits.
4.3.1.1
Interrupt Vector Base Register (IVBR)
Address: 0x0120
7
6
5
4
3
2
1
0
R
W
IVB_ADDR[7:0]
Reset
1
1
1
1
1
1
1
1
Figure 4-2. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
125
FREESCALE [ Freescale ]
