Memory Map Control (S12PMMCV1)
Global Address [17:0]
Bit14 Bit13
Bit17
Bit0
PPAGE Register [3:0]
Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 3-8. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
Table 3-7. PPAGE Field Descriptions
Description
Field
3–0
Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 P-Flash or ROM
PIX[3:0]
array pages is to be accessed in the Program Page Window.
The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0x0C. Parts of this page are covered by
Registers, D-Flash and RAM space. See SoC Guide for details.
The fixed 16KB page from 0x4000–0x7FFF is the page number 0x0D.
The reset value of 0x0E ensures that there is linear Flash space available between addresses 0x0000 and
0xFFFF out of reset.
The fixed 16KB page from 0xC000-0xFFFF is the page number 0x0F.
3.4
Functional Description
The S12PMMC block performs several basic functions of the S12I sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
3.4.1
MCU Operating Modes
•
Normal single chip mode
This is the operation mode for running application codeThere is no external bus in this mode.
Special single chip mode
•
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
113
FREESCALE [ Freescale ]
