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MC908AP32CFAE 参数 Datasheet PDF下载

MC908AP32CFAE图片预览

型号：	MC908AP32CFAE
PDF下载：	下载PDF文件查看货源
内容描述：	[MC908AP32CFAE]
分类和应用：
文件页数/大小：	325 页 / 4102 K
品牌：	FREESCALE [ Freescale ]

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Table 4-2. Opcode Map

Bit Manipulation Branch

Read-Modify-Write

Control

Register/Memory

DIR

DIR

REL

DIR

3

INH

4

INH

IX1

SP1

9E6

IX

7

INH

INH

IMM

A

DIR

B

EXT

C

IX2

SP2

IX1

E

SP1

9EE

IX

F

MSB

0

1

2

5

6

8

9

D

9ED

LSB

5

4

3

4

1

NEGA

INH

1

NEGX

INH

4

5

3

7

3

2

3

4

4

5

3

4

2

0

BRSET0 BSET0

BRA

NEG

NEG

NEG

NEG

IX

RTI

BGE

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

IX

3

DIR

5

2

DIR

4

2

2

2

2

2

2

2

2

REL 2 DIR

1

1

2

IX1 3 SP1

5

1

2

1

1

1

2

1

1

1

1

1

2

1

1

2

1

1

1

INH

2

2

2

2

1

1

REL 2 IMM 2 DIR

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

EXT 3 IX2

4

4

4

4

4

4

4

4

4

4

4

4

SP2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

IX1

3

3

3

3

3

3

3

3

3

3

3

3

SP1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

3

BRN

REL 3 DIR

5

4

4

6

4

CBEQ

IX+

2

DAA

INH

3

COM

IX

3

LSR

IX

4

CPHX

DIR

3

ROR

IX

3

ASR

IX

3

LSL

IX

3

ROL

IX

3

DEC

IX

4

DBNZ

IX

3

INC

IX

4

3

BLT

2

CMP

3

CMP

4

CMP

EXT 3 IX2

4

SBC

EXT 3 IX2

4

CPX

EXT 3 IX2

4

AND

EXT 3 IX2

4

BIT

EXT 3 IX2

4

LDA

EXT 3 IX2

4

STA

EXT 3 IX2

4

EOR

EXT 3 IX2

4

ADC

EXT 3 IX2

4

ORA

EXT 3 IX2

4

ADD

EXT 3 IX2

3

JMP

EXT 3 IX2

5

JSR

EXT 3 IX2

4

LDX

EXT 3 IX2

4

STX

EXT 3 IX2

4

CMP

5

3

4

2

CMP

IX

2

SBC

IX

2

CPX

IX

2

AND

IX

2

BIT

IX

2

LDA

IX

2

STA

IX

2

EOR

IX

2

ADC

IX

2

ORA

IX

2

ADD

IX

2

JMP

IX

4

JSR

IX

2

LDX

IX

2

STX

IX

1

2

BRCLR0 BCLR0

CBEQ CBEQA CBEQX CBEQ

CBEQ

RTS

CMP

CMP

CMP

3

DIR

5

2

DIR

4

3

1

IMM 3 IMM 3 IX1+

4

SP1

INH

REL 2 IMM 2 DIR

SP2

IX1

SP1

3

5

7

3

3

BGT

2

SBC

3

SBC

4

SBC

5

3

4

BRSET1 BSET1

BHI

MUL

DIV

INH

NSA

SBC

SBC

SBC

3

DIR

5

2

DIR

4

REL

INH

1

1

2

2

3

2

2

2

2

2

INH

REL 2 IMM 2 DIR

SP2

IX1

SP1

3

BLS

REL 2 DIR

3

BCC

REL 2 DIR

3

BCS

REL 2 DIR

3

BNE

REL 2 DIR

4

1

1

4

COM

IX1

4

LSR

IX1

3

CPHX

IMM

4

ROR

IX1

4

ASR

IX1

4

LSL

IX1

4

ROL

IX1

4

DEC

IX1

5

9

3

BLE

2

CPX

3

CPX

4

CPX

5

3

4

3

BRCLR1 BCLR1

COM

COMA

COMX

COM

SWI

CPX

CPX

CPX

3

DIR

5

2

DIR

4

1

INH

1

INH

3

3

SP1

1

1

1

1

1

1

1

1

1

1

INH

REL 2 IMM 2 DIR

SP2

IX1

SP1

4

LSR

1

LSRA

INH

1

LSRX

INH

5

2

2

2

AND

IMM 2 DIR

3

AND

4

AND

5

3

4

4

BRSET2 BSET2

LSR

TAP

TXS

AND

AND

AND

3

DIR

5

2

DIR

4

1

3

1

SP1

INH

INH

2

2

2

2

2

2

2

2

SP2

IX1

SP1

4

3

4

1

2

2

BIT

3

BIT

4

BIT

5

3

4

5

BRCLR2 BCLR2

STHX

LDHX

LDHX

TPA

TSX

BIT

BIT

BIT

3

DIR

5

2

DIR

4

IMM 2 DIR

INH

INH

IMM 2 DIR

SP2

IX1

SP1

4

ROR

1

1

5

2

PULA

INH

2

PSHA

INH

2

PULX

INH

2

PSHX

INH

2

PULH

INH

2

PSHH

INH

1

CLRH

INH

2

LDA

IMM 2 DIR

2

AIS

IMM 2 DIR

2

EOR

IMM 2 DIR

2

ADC

IMM 2 DIR

2

ORA

IMM 2 DIR

2

ADD

IMM 2 DIR

3

LDA

4

LDA

5

3

4

6

BRSET3 BSET3

RORA

RORX

ROR

LDA

LDA

LDA

3

DIR

5

2

DIR

4

1

INH

1

INH

3

3

3

3

3

4

3

3

SP1

5

SP2

IX1

SP1

3

BEQ

REL 2 DIR

3

4

ASR

1

ASRA

INH

1

LSLA

INH

1

ROLA

INH

1

DECA

INH

1

ASRX

INH

1

LSLX

INH

1

ROLX

INH

1

DECX

INH

1

3

STA

4

STA

5

3

4

7

BRCLR3 BCLR3

ASR

TAX

STA

STA

STA

3

DIR

5

2

DIR

4

1

1

1

1

1

1

1

1

SP1

5

1

1

1

1

1

1

1

INH

SP2

IX1

SP1

4

LSL

1

3

EOR

4

EOR

5

3

4

8

BRSET4 BSET4 BHCC

LSL

CLC

EOR

EOR

EOR

3

DIR

5

2

DIR

4

2

REL 2 DIR

3

SP1

5

INH

SP2

IX1

SP1

4

ROL

1

3

ADC

4

ADC

5

3

4

9

BRCLR4 BCLR4 BHCS

ROL

SEC

ADC

ADC

ADC

3

DIR

5

2

DIR

4

2

2

2

2

2

2

2

REL 2 DIR

SP1

5

INH

SP2

IX1

SP1

3

BPL

REL 2 DIR

3

BMI

REL 3 DIR

3

BMC

REL 2 DIR

4

DEC

2

3

ORA

4

ORA

5

3

4

A

B

C

D

E

F

BRSET5 BSET5

DEC

CLI

ORA

ORA

ORA

3

DIR

5

2

DIR

4

SP1

6

INH

SP2

IX1

SP1

5

3

3

5

2

3

ADD

4

ADD

5

3

4

BRCLR5 BCLR5

DBNZ DBNZA DBNZX DBNZ

DBNZ

SEI

ADD

ADD

ADD

3

DIR

5

2

DIR

4

2

1

1

3

1

INH

1

2

1

1

2

1

INH

1

3

2

2

3

2

IX1

4

SP1

5

INH

SP2

IX1

SP1

4

INC

1

2

JMP

4

JMP

3

BRSET6 BSET6

INCA

INCX

INC

INC

RSP

JMP

3

DIR

5

2

DIR

4

INH

1

INH

1

IX1

3

SP1

4

INH

2

DIR

4

IX1

3

BMS

3

TST

2

TST

IX

1

4

BSR

REL 2 DIR

2

LDX

IMM 2 DIR

2

AIX

IMM 2 DIR

6

JSR

5

BRCLR6 BCLR6

TSTA

TSTX

TST

TST

NOP

JSR

JSR

3

DIR

5

2

DIR

4

REL 2 DIR

3

INH

5

INH

4

IX1

4

SP1

INH

2

2

2

IX1

4

1

STOP

INH

1

WAIT

INH

3

LDX

4

LDX

5

3

4

BRSET7 BSET7

BIL

MOV

MOV

MOV

MOV

IX+D

LDX

LDX

LDX

*

1

TXA

INH

3

DIR

5

2

DIR

4

REL

3

DD

DIX+

IMD

3

1

1

4

4

SP2

IX1

3

3

SP1

3

CLR

1

CLRA

INH

1

CLRX

INH

4

2

CLR

IX

3

STX

4

STX

5

3

4

BRCLR7 BCLR7

BIH

CLR

CLR

SP1

STX

STX

STX

3

DIR

2

DIR

REL 2 DIR

IX1

3

1

SP2

IX1

SP1

INH Inherent

REL Relative

SP1 Stack Pointer, 8-Bit Offset

SP2 Stack Pointer, 16-Bit Offset

IX+ Indexed, No Offset with

Post Increment

IX1+ Indexed, 1-Byte Offset with

Post Increment

MSB

LSB

0

High Byte of Opcode in Hexadecimal

Cycles

IMM Immediate

DIR Direct

IX

Indexed, No Offset

IX1 Indexed, 8-Bit Offset

IX2 Indexed, 16-Bit Offset

IMD Immediate-Direct

EXT Extended

DD Direct-Direct

IX+D Indexed-Direct DIX+ Direct-Indexed

*Pre-byte for stack pointer indexed instructions

5

Low Byte of Opcode in Hexadecimal

0

BRSET0 Opcode Mnemonic

DIR Number of Bytes / Addressing Mode

3

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