Opcode Map
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
STX opr
STX opr
DIR
EXT
IX2
– IX1
IX
BF
CF
DF
EF
FF
dd
3
4
4
3
2
4
5
hh ll
ee ff
ff
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
–
o
o
SP1
SP2
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Subtract
A ← (A) – (M)
o
o o o
9EE0 ff
9ED0 ee ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
o
–
–
o
–
–
o
–
–
o
–
–
o
–
–
o INH
– INH
– INH
84
97
85
2
1
1
Transfer CCR to A
A ← (CCR)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
3
1
1
3
2
4
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
o
o
–
SP1
9E6D ff
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
I ← 0; Inhibit CPU clocking until
WAIT
Enable Interrupts; Wait for Interrupt
–
–
0
–
–
– INH
8F
1
interrupted
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
67
FREESCALE [ Freescale ]
