Central Processor Unit (CPU)
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
A
C
Accumulator
Carry/borrow bit
n
opr
PC
Any bit
Operand (one or two bytes)
Program counter
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DD
DIR
DIX+ Direct to indexed with post increment addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
Direct to direct addressing mode
Direct addressing mode
Relative program counter offset byte
Relative program counter offset byte
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
ff
H
H
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
SP
U
V
Stack pointer
Undefined
Overflow bit
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
X
Z
Index register low byte
Zero bit
ii
Immediate operand byte
&
Logical AND
IMD
Immediate source to direct destination addressing mode
|
Logical OR
IMM Immediate addressing mode
⊕
Logical EXCLUSIVE OR
Contents of
INH
IX
IX+
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
( )
–( ) Negation (two’s complement)
#
«
←
?
Immediate value
Sign extend
Loaded with
If
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
IX2
M
N
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
:
o
—
Concatenated with
Set or cleared
Not affected
MC68HC908AP Family Data Sheet, Rev. 4
68
Freescale Semiconductor
FREESCALE [ Freescale ]
