Clock Selection
Table 5-1. CGMXCLK Clock Selection
OSCSEL1
OSCSEL0
CGMXCLK
—
OSC2 Pin
—
Comments
0
0
0
1
Not used
fBUS
ICLK
Internal oscillator generates the CGMXCLK.
RC oscillator generates the CGMXCLK.
Internal oscillator is available after each POR or
reset.
fBUS
1
1
0
1
RCCLK
XCLK
Inverting
output of
X-TAL
X-tal oscillator generates the CGMXCLK.
Internal oscillator is available after each POR or
reset.
NOTE
The internal oscillator is a free running oscillator and is available after each
POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS
bit in CONFIG2.
5.2.2 TBM Reference Clock Selection
The timebase module reference clock (OSCCLK) is selected by configuring two bits in the CONFIG2
register, at $001D. See Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR).
Address:
$001D
Bit 7
6
5
4
3
2
0
1
0
Bit 0
Read:
Write:
Reset:
STOP_
ICLKDIS
STOP_ STOP_
RCLKEN XCLKEN
SCIBD-
SRC
OSCCLK1 OSCCLK0
0
0
0
0
0
0
0
0
Figure 5-3. Configuration Register 2 (CONFIG2)
Table 5-2. Timebase Module Reference Clock Selection
OSCCLK1
OSCCLK0
Timebase Clock Source
Internal oscillator (ICLK)
RC oscillator (RCCLK)
X-tal oscillator (XCLK)
Not used
0
0
1
1
0
1
0
1
NOTE
The RCCLK or XCLK is only available if that clock is selected as the CGM
reference clock, whereas the ICLK is always available.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
73
FREESCALE [ Freescale ]
