Configuration Register 1 (CONFIG1)
LVIPWRD — V LVI Circuit Disable Bit
DD
LVIPWRD disables the V LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).)
DD
1 = V LVI circuit disabled
DD
0 = V LVI circuit enabled
DD
LVIREGD — V
LVI Circuit Disable Bit
REG
LVIREGD disables the V
LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).)
REG
1 = V
0 = V
LVI circuit disabled
LVI circuit enabled
REG
REG
NOTE
If LVIPWRD=1 and LVIREGD=1, set LVIRSTD=1 before entering stop
mode.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK
cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
When the LVI is disabled in stop mode (LVISTOP=0), the system
stabilization time for long stop recovery (4096 ICLK cycles) gives a delay
longer than the LVI’s turn-on time. There is no period where the MCU is not
protected from a low power condition. However, when using the short stop
recovery configuration option, the 32 ICLK delay is less than the LVI’s
turn-on time and there exists a period in start-up where the LVI is not
protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 19 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
51
FREESCALE [ Freescale ]
