Chapter 3
Configuration & Mask Option Registers (CONFIG & MOR)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option
register, MOR.
The configuration registers enable or disable these options:
•
•
•
•
•
•
•
•
•
•
Computer operating properly module (COP)
18
4
13
4
COP timeout period (2 – 2 or 2 – 2 ICLK cycles)
Low-voltage inhibit (LVI) on V
DD
LVI on V
REG
LVI module reset
LVI module in stop mode
STOP instruction
Stop mode recovery time (32 ICLK or 4096 ICLK cycles)
Oscillator (internal, RC, and crystal) during stop mode
Serial communications interface clock source (CGMXCLK or f
)
BUS
The mask option register selects one of the following oscillator options:
•
•
•
Internal oscillator
RC oscillator
Crystal oscillator
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Configuration Register 2 Read:
(CONFIG2)†
Write:
0
0
STOP_
ICLKDIS
STOP_ STOP_
RCLKEN XCLKEN
OSCCLK1 OSCCLK0
SCIBDSRC
$001D
Reset:
0
COPRS
0
0
0
0
0
0
0
0
Read:
Configuration Register 1
LVISTOP LVIRSTD LVIPWRD LVIREGD
SSREC
STOP
COPD
$001F
$FFCF
Write:
(CONFIG1)†
Reset:
0
0
R
1
0
R
1
0
R
1
0
R
1
0
R
1
0
R
1
Mask-Option-Register Read:
(MOR)#
Write:
OSCSEL1 OSCSEL0
Erased:
1
1
† One-time writable register after each reset.
# MOR is a non-volatile FLASH register; write by programming.
= Unimplemented
R
= Reserved
Figure 3-1. CONFIG and MOR Registers Summary
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
49
FREESCALE [ Freescale ]
