Input/Output (I/O) Ports
PTC[7:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
IRQ2 — IRQ2 input pin
The PTC0/IRQ2 pin is always available as input pin to the IRQ2 module. Care must be taken to
available unwanted interrupts when this pin is used as general purpose I/O. PTC0/IRQ2 pin has an
internal pullup, and can be disabled by setting the PUC0ENB bit in the IRQ2 status and control register
(INTSCR2).
MISO, MOSI, SS, and SPSCK — SPI Data I/O, Select, and Clock Pins
These pins are the SPI data in/out, select, and clock pins. Setting the SPE bit in the SPI control register
(SPCR) configures PTC2/MISO, PTC3/MOSI, PTC4/SS, and PTC5/SPSCK pins for SPI function and
overrides any control from the port I/O logic.
SCTxD and SCRxD — IrSCI Transmit and Receive Data
The SCTxD and SCRxD pins are IRSCI transmit and receive data pins. Setting the ENSCI bit in the
IRSCI control register 1 (IRSCC1) configures the PTC6/SCTxD and PTC7/SCRxD pins for IRSCI
function and overrides any control from the port I/O logic.
16.4.2 Data Direction Register C (DDRC)
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
Address:
$0006
Bit 7
6
DDRC6
0
5
DDRC5
0
4
DDRC4
0
3
DDRC3
0
2
DDRC2
0
1
DDRC1
0
Bit 0
DDRC0
0
Read:
Write:
Reset:
DDRC7
0
Figure 16-10. Data Direction Register C (DDRC)
DDRC[7:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 16-11 shows the port C I/O logic.
NOTE
For those devices packaged in a 42-pin shrink dual in-line package, PTC0
and PTC1 are not connected. DDRC0 and DDRC1 should be set to a 1 to
configure PTC0 and PTC1 as outputs.
MC68HC908AP Family Data Sheet, Rev. 4
266
Freescale Semiconductor
FREESCALE [ Freescale ]
