Port C
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
PTBx
RESET
WRITE PTB ($0001)
READ PTB ($0001)
#
PTBx
# PTB3–PTB0 are open-drain pins when configured as outputs.
PTB7–PTB4 have schmitt trigger inputs.
Figure 16-8. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 16-3 summarizes the operation of the port B pins.
Table 16-3. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
DDRB
Bit
PTB Bit
I/O Pin Mode
Read
Pin
Write
X(1)
X
Input, Hi-Z(2)
Output
PTB[7:0](3)
PTB[7:0]
0
1
DDRB[7:0]
DDRB[7:0]
PTB[7:0]
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
16.4 Port C
Port C is an 8-bit special-function port that shares one of its pins with the IRQ2, four of its pins with the
SPI module, and two of its pins with the IRSCI module.
16.4.1 Port C Data Register (PTC)
The port C data register contains a data latch for each of the eight port C pins.
Address:
$0002
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Unaffected by reset
SS MOSI
Alternative Function: SCRxD
SCTxD
SPSCK
MISO
IRQ2
Figure 16-9. Port C Data Register (PTC)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
265
FREESCALE [ Freescale ]
