Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
CGMOUT ÷ 2
FROM SIM
MISO
7
6
5
4
3
2
1
0
÷ 2
MOSI
÷ 8
÷ 32
CLOCK
DIVIDER
RECEIVE DATA REGISTER
PIN
CONTROL
LOGIC
÷ 128
CLOCK
SPSCK
SS
SPMSTR SPE
SELECT
M
S
CLOCK
LOGIC
SPR1
SPR0
SPMSTR CPHA
CPOL
RESERVED
MODFEN
ERRIE
SPTIE
SPRIE
R
SPWOM
TRANSMITTER CPU INTERRUPT REQUEST
RESERVED
SPI
CONTROL
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPE
SPRF
SPTE
OVRF
MODF
Figure 13-2. SPI Module Block Diagram
MASTER MCU
SLAVE MCU
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SPSCK
SS
SPSCK
SS
BAUD RATE
GENERATOR
V
DD
Figure 13-3. Full-Duplex Master-Slave Connections
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
211
FREESCALE [ Freescale ]
