Serial Peripheral Interface Module (SPI)
=
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SPE
0
Bit 0
SPTIE
0
Read:
SPRIE
R
0
SPMSTR
CPOL
CPHA
SPWOM
0
$0010 SPI Control Register (SPCR) Write:
Reset:
0
1
0
1
Read:
SPRF
OVRF
MODF
SPTE
SPI Status and Control
ERRIE
MODFEN
SPR1
SPR0
$0011
$0012
Register Write:
(SPSCR)
Reset:
Read:
Write:
Reset:
0
0
0
0
1
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR)
Unaffected by reset
R
= Unimplemented
= Reserved
Figure 13-1. SPI I/O Register Summary
13.4 Functional Description
Figure 13-2 shows the structure of the SPI module.
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven.
The following paragraphs describe the operation of the SPI module.
13.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. (See 13.13.1 SPI Control Register.)
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. (See Figure 13-3.)
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See 13.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
MC68HC908AP Family Data Sheet, Rev. 4
210
Freescale Semiconductor
FREESCALE [ Freescale ]
