Queuing Transmission Data
WRITE
TO SPDR
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 6
BIT 5
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
BUS
CLOCK
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
EARLIEST
LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 8;
LATEST
LATEST
LATEST
8 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
Figure 13-7. Transmission Start Delay (Master)
13.6 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 13-8 shows
the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL =
1:0).
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
215
FREESCALE [ Freescale ]
