Freescale Semiconductor, Inc.
Capture/Compare Timer
8.4.2 Timer Status Register
The timer status register (TSR) is a read-only register shown in
Figure 8-6 contains flags for these events:
• An active signal on the TCAP pin, transferring the contents of the
timer registers to the input capture registers
• A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
• A timer rollover from $FFFF to $0000
Address: $0013
Bit 7
ICF
6
5
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
OCF
TOF
U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 8-6. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Reset has no effect on ICF.
1 = Input capture
0 = No input capture
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Reset has no
effect on OCF.
1 = Output compare
0 = No output compare
Technical Data
96
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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