Freescale Semiconductor, Inc.
Capture/Compare Timer
8.4.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers (ICRH and ICRL) shown in Figure 8-11. Reading ICRH before
reading ICRL inhibits further captures until ICRL is read. Reading ICRL
after reading the timer status register clears the input capture flag (ICF).
Writing to the input capture registers has no effect.
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Register Name and Address: Input Capture Register High — $0014
Read: Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Unaffected by reset
Register Name and Address: Input Capture Register Low — $0015
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unaffected by reset
= Unimplemented
Figure 8-11. Input Capture Registers (ICRH and ICRL)
NOTE: To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt mask (I bit) in the condition code register before
reading ICRH and clear the mask after reading ICRL.
Technical Data
100
MC68HC705C8A — Rev. 3
Capture/Compare Timer
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