Freescale Semiconductor, Inc.
Interrupts
Interrupt Sources
4.3.3 Port B Interrupts
When these three conditions are true, a port B pin (PBx) acts as an
external interrupt pin:
• The corresponding port B pullup bit (PBPUx) in mask option
register 1 (MOR1) is programmed to a logic 1.
• The corresponding port B data direction bit (DDRBx) in data
direction register B (DDRB) is a logic 0.
• The clear interrupt mask (CLI) instruction has cleared the I bit in
the CCR.
MOR1 is an erasable, programmable read-only memory (EPROM)
register that enables the port B pullup device. Data from MOR1 is
latched on the rising edge of the voltage on the RESET pin. See 9.5.2
Mask Option Register 1.
Port B external interrupt pins can be falling-edge sensitive only or both
falling-edge and low-level sensitive, depending on the state of the IRQ
bit in the option register at location $1FDF.
When the IRQ bit is a logic 1, a falling edge or a low level on a port B
external interrupt pin latches an external interrupt request. As long as
any port B external interrupt pin is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service routine.
When the IRQ bit is a logic 0, a falling-edge only on a port B external
interrupt pin latches an external interrupt request. A subsequent port B
external interrupt request can be latched only after the voltage level of
the previous port B external interrupt signal returns to a logic 1 and then
falls again to a logic 0.
Figure 4-3 shows the port B input/output (I/O) logic.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Interrupts
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