Freescale Semiconductor, Inc.
Interrupts
EDGE- AND LEVEL-SENSITIVE TRIGGER
OPTION REGISTER
V
DD
EXTERNAL
INTERRUPT
REQUEST
D
Q
I BIT (CCR)
IRQ LATCH
INTERRUPT PIN
C
Q
POR
R
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VECTOR FETCH)
Figure 4-1. External Interrupt Internal Function Diagram
tILIL
t
IRQ PIN
ILIH
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t ) is either 125 ns (f = 2.1 MHz)
ILIH
OP
or 250 ns (f = 1 MHz). The period t
should not be less than the number of t cycles it takes to
OP
ILIL
CYC
execute the interrupt service routine plus 19 t
cycles.
CYC
tILIH
IRQ1
.
.
.
NORMALLY
USED WITH
WIRED-OR
IRQn
CONNECTION
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If the interrupt line remains low after servicing an interrupt, then the
CPU continues to recognize an interrupt.
Figure 4-2. External Interrupt Timing
Technical Data
52
MC68HC705C8A — Rev. 3
Interrupts
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