Freescale Semiconductor, Inc.
Interrupts
Interrupt Sources
4.3.2 External Interrupt (IRQ)
An interrupt signal on the IRQ pin latches an external interrupt request.
After completing the current instruction, the CPU tests these bits:
• IRQ latch
• I bit in the CCR
Setting the I bit in the CCR disables external interrupts.
If the IRQ latch is set and the I bit is clear, the CPU then begins the
interrupt sequence. The CPU clears the IRQ latch while it fetches the
interrupt vector, so that another external interrupt request can be latched
during the interrupt service routine. As soon as the I bit is cleared during
the return-from-interrupt (RTI) instruction, the CPU can recognize the
new interrupt request. Figure 4-1 shows the logic for external interrupts.
Figure 4-1 shows an external interrupt functional diagram. Figure 4-2
shows an external interrupt timing diagram for the interrupt line. The
timing diagram illustrates two treatments of the interrupt line to the
processor.
1. Two single pulses on the interrupt line are spaced far enough
apart to be serviced. The minimum time between pulses is a
function of the length of the interrupt service.
Once a pulse occurs, the next pulse normally should not occur
until an RTI occurs. This time (tILIL) is obtained by adding 19
instruction cycles to the total number of cycles needed to complete
the service routine (not including the RTI instruction).
2. Many interrupt lines are “wire-ORed” to the IRQ line. If the interrupt
line remains low after servicing an interrupt, then the CPU
continues to recognize an interrupt.
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine. Therefore, a new external interrupt pulse could be
latched and serviced as soon as the I bit is cleared.
If the IRQ pin is not in use, connect it to the VDD pin.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Interrupts
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