Freescale Semiconductor, Inc.
Capture/Compare Timer
Timer I/O Registers
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL) shown in Figure 8-12, the
planned TCMP pin action takes place. Writing to OCRH before writing to
OCRL inhibits timer compares until OCRL is written. Reading or writing
to OCRL after reading the timer status register clears the output
compare flag (OCF).
Bit 7
6
5
4
3
2
1
Bit 0
Register Name and Address: Output Compare Register High — $0016
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Unaffected by reset
Register Name and Address: Output Compare Register Low — $0017
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 8-12. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
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