Freescale Semiconductor, Inc.
Configuration Register (CONFIG-1)
Functional Description
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. See
9.7.2 Stop Mode.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPL — COP Long Timeout Bit
COPL enables the shorter COP timeout period. See Section 14.
Computer Operating Properly (COP) Module.
1 = COP timeout period is 8,176 CGMXCLK cycles.
0 = COP timeout period is 262,128 CGMXCLK cycles.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Section 14. Computer
Operating Properly (COP) Module.
1 = COP module disabled
0 = COP module enabled
WARNING: Extra care should be exercised when using this emulation part for
development of code to be run in ROM-based M68HC08AS Family
parts that the options selected by setting the CONFIG-1 register
match exactly the options selected on any ROM code request
submitted. The enable/disable logic is not necessarily identical in
all parts of the AS Family. If there is any doubt, check with a local
field applications representative.
MC68HC908AS60 — Rev. 1.0
Technical Data
Configuration Register (CONFIG-1)
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