Freescale Semiconductor, Inc.
Configuration Register (CONFIG-1)
Address: $001F
Bit 7
6
5
4
3
2
COPL
0
1
STOP
0
Bit 0
COPD
0
Read:
LVISTOP
Write:
R
LVIRST LVIPWR SSREC
Reset:
0
1
1
1
0
R
=Reserved
Figure 11-1. Configuration Write-Once Register (CONFIG-1)
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. See Section 15.
Low-Voltage Inhibit (LVI) Module.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE: To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop IDD current will be higher and for compatibility
when using a MC68HC08AS20 a register bit will have to be written. See
the LVI section of the MC68HC08AS20 Advance Information (Motorola
document order number MC68HC08AS20/D.)
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See
Section 15. Low-Voltage Inhibit (LVI) Module.
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. See Section 15. Low-Voltage
Inhibit (LVI) Module.
1 = LVI module power enabled
0 = LVI module power disabled
Technical Data
MC68HC908AS60 — Rev. 1.0
Configuration Register (CONFIG-1)
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