Freescale Semiconductor, Inc.
Break Module
Functional Description
Addr.
Register Name
Bit 7
Bit 15
0
6
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
1
Bit 0
Bit 8
0
Read:
Break Address Register High
14
$FE0C
(BRKH) Write:
See page 190.
Reset:
Read:
0
Break Address Register Low
Bit 7
0
6
5
4
3
2
Bit 0
$FE0D
$FE0E
(BRKL) Write:
See page 190.
Reset:
Read:
0
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
Break Status and Control
BRKE
0
Register (BSCR) Write:
See page 189.
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 12-2. I/O Register Summary
12.4.1 Flag Protection During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
12.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
12.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
MC68HC908AS60 — Rev. 1.0
Technical Data
Break Module
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