Freescale Semiconductor, Inc.
System Integration Module (SIM)
Program Exception Control
9.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
CONFIG-1 register. If the SSREC bit is a logic 1, then the stop recovery
is reduced from the normal delay of 4096 CGMXCLK cycles down to
32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long startup times from stop mode.
External crystal applications should use the full stop recovery time, that
is, with SSREC cleared.
9.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 9.7.2 Stop Mode
for details). The SIM counter is free-running after all reset states. See
9.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
9.6 Program Exception Control
Normal, sequential program execution can be changed in three different
ways:
1. Interrupts:
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
3. Break interrupts
9.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 9-8 shows interrupt entry timing.
Figure 9-9 shows interrupt recovery timing.
MC68HC908AS60 — Rev. 1.0
Technical Data
System Integration Module (SIM)
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