Freescale Semiconductor, Inc.
System Integration Module (SIM)
Reset and System Initialization
9.4.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See Table 9-2 for details.
Figure 9-4 shows the relative timing.
Table 9-2. PIN Bit Set Timing
Reset Type
POR/LVI
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
CGMOUT
RST
VECT H VECT L
IAB
PC
Figure 9-4. External Reset Timing
9.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. See
Figure 9-5. An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. See Figure 9-6 . Note that for LVI
or POR resets, the SIM cycles through 4096 CGMXCLK cycles during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 9-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
MC68HC908AS60 — Rev. 1.0
Technical Data
System Integration Module (SIM)
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