Freescale Semiconductor, Inc.
System Integration Module (SIM)
indexed addressing and PUL/PSH instructions will also generate an
illegal address reset.
WARNING: Extra care should be exercised when using this emulator part for
development of code to be run in ROM-based M68HC08AS Family
parts with a smaller memory size since some legal addresses will
become illegal addresses on the smaller ROM memory map device
and may, as a result, generate unwanted resets.
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the VDD voltage falls to the VLVII voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG-1 register are at logic 0. The RST pin
will be held low until the SIM counts 4096 CGMXCLK cycles after VDD
rises above VLVIR. Another 64 CGMXCLK cycles later, the CPU is
released from reset to allow the reset vector sequence to occur.
See Section 15. Low-Voltage Inhibit (LVI) Module.
9.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
9.5.1 SIM Counter During Power-On Reset
The POR detects power applied to the MCU. At power-on, the POR
circuit asserts the signal PORRST. Once the SIM is initialized, it enables
the clock generation module (CGM) to drive the bus clock state machine.
Technical Data
MC68HC908AS60 — Rev. 1.0
System Integration Module (SIM)
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