Freescale Semiconductor, Inc.
System Integration Module (SIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
See Note
0
Bit 0
Read:
SIM Break Status Register
R
R
R
R
R
R
R
$FE00
(SBSR) Write:
See page 151.
Reset:
Read: POR
PIN
COP
ILOP
ILAD
0
LVI
0
SIM Reset Status Register
(SRSR) Write:
$FE01
$FE03
See page 153.
Reset:
Read:
1
BCFE
0
0
0
0
0
0
0
0
SIM Break Flag Control
R
R
R
R
R
R
R
Register (SBFCR) Write:
See page 154.
Reset:
Note: Writing a logic 0 clears SBSW.
= Unimplemented
R
= Reserved
Figure 9-2. SIM I/O Register Summary
Table 9-1 shows the internal signal names used in this section.
Table 9-1. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from clock generator
module (CGM)
CGMOUT
Bus clock = CGMOUT divided by two
IAB
IDB
Internal address bus
Internal data bus
PORRST
IRST
Signal from the power-on reset (POR) module to the SIM
Internal reset signal
R/W
Read/write signal
Technical Data
MC68HC908AS60 — Rev. 1.0
System Integration Module (SIM)
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