Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 8-1. Instruction Set Summary (Sheet 4 of 8)
Effect on CCR
e
s
Source
Form
Operation
Description
o
d
e
V H I N Z C
M
C
O cp
d
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
ff
4
1
1
4
3
5
Complement (One’s
Complement)
0
–
–
–
↕ ↕ 1
COM opr,SP
SP1
9E63 ff
ii
65
75
CPHX #opr
CPHX opr
IMM
DIR
ii+
1
3
4
Compare H:X with M
(H:X) – (M:M + 1)
↕ –
↕ ↕ ↕
dd
CPX #opr
CPX opr
CPX opr
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
3
4
4
3
2
4
5
B3 dd
C3 hh ll
D3 ee ff
E3 ff
CPX ,X
Compare X with M
Decimal Adjust A
(X) – (M)
↕ –
–
↕ ↕ ↕
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
F3
SP1
SP2
9EE3 ff
9ED3 ee ff
(A)10
DAA
U
–
–
–
–
–
↕ ↕ ↕ INH
72
2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
INH
IX1
IX
3B dd rr
4B rr
5B rr
6B ff rr
7B rr
9E6B ff rr
Decrement and Branch if Not
Zero
–
–
–
SP1
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A dd
4A
5A
6A ff
7A
9E6A ff
4
1
1
4
3
5
Decrement
Divide
↕ –
–
–
↕ ↕ –
SP1
A ← (H:A)/(X)
H ← Remainder
DIV
–
0
–
–
–
↕ ↕ INH
52
7
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
Exclusive OR M with A
–
–
↕ ↕ –
A ← (A
M)
F8
SP1
SP2
9EE8 ff
9ED8 ee ff
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
5C
6C ff
7C
9E6C ff
4
1
1
4
3
5
Increment
↕ –
↕ ↕ –
SP1
Technical Data
MC68HC908AS60 — Rev. 1.0
Central Processor Unit (CPU)
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