Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 8-1. Instruction Set Summary (Sheet 2 of 8)
Effect on CCR
e
s
Source
Form
Operation
Description
o
d
e
V H I N Z C
M
C
O cp
d
Branch if Carry Bit Set
(Same as BLO)
BCS rel
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
REL
25
27
90
rr
rr
rr
3
3
3
BEQ rel
Branch if Equal
Branch if Greater Than or
Equal To (Signed Operands)
BGE opr
PC ← (PC) + 2 + rel ? (N
V) = 0
Branch if Greater Than (Signed
Operands)
BGT opr
–
–
–
–
–
–
REL
92
rr
3
3
PC ← (PC) + 2 + rel ? (Z) | (N V) = 0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
REL
28
29
22
rr
rr
rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
REL
24
2F
rr
rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
3
3
2E rr
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
Bit Test
(A) & (M)
0
–
–
↕ ↕ –
F5
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal
To (Signed Operands)
BLE opr
–
–
–
–
–
–
REL
93
rr
3
PC ← (PC) + 2 + rel ? (Z) | (N
V) = 1
BLO rel
BLS rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
25
23
rr
rr
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
Branch if Less Than (Signed
Operands)
BLT opr
–
–
–
–
–
–
REL
91
rr
3
PC ← (PC) + 2 + rel ? (N
V) =1
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
REL
REL
REL
REL
2C rr
2B rr
2D rr
3
3
3
3
3
3
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
26
rr
2A rr
Branch Always
20
rr
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
–
–
–
–
–
↕
0B dd rr
0D dd rr
0F
dd rr
Technical Data
MC68HC908AS60 — Rev. 1.0
Central Processor Unit (CPU)
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