Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 8-1. Instruction Set Summary (Sheet 8 of 8)
Effect on CCR
e
s
Source
Form
Operation
Description
o
d
e
V H I N Z C
M
C
O cp
d
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D dd
4D
5D
6D ff
7D
9E6D ff
3
1
1
3
2
4
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
↕ ↕ –
TST opr,SP
SP1
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
INH
INH
INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
A
Accumulator
n
Any bit
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
H
H
hh ll
I
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
V
X
Z
Overflow bit
Index register low byte
Zero bit
ii
Immediate operand byte
Immediate source to direct destination addressing mode
&
|
Logical AND
Logical OR
IMD
IMM
INH
IX
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
( )
–( )
#
IX+
IX+D
IX1
IX1+
IX2
M
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
«
←
?
:
↕
—
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
N
Negative bit
8.9 Opcode Map
The opcode map is provided in Table 8-2.
Technical Data
MC68HC908AS60 — Rev. 1.0
Central Processor Unit (CPU)
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