Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set Summary
Table 8-1. Instruction Set Summary (Sheet 1 of 8)
s
d
Effect on CCR
s
Source
Form
Operation
Description
d
c
V H I N Z C
M
Cyc
O
A
Ope
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
Add with Carry
A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕
F9
SP1
SP2
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
2
3
4
4
3
2
4
5
Add without Carry
A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕
FB
SP1
SP2
9EEB ff
9EDB ee ff
Add Immediate Value (Signed)
to SP
AIS #opr
AIX #opr
–
–
–
–
–
–
–
–
–
–
–
–
IMM
IMM
A7 ii
AF ii
2
2
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
Add Immediate Value (Signed
to H:X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
Logical AND
A ← (A) & (M)
0
–
–
–
↕ ↕ –
F4
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
C
0
↕ –
↕ ↕ ↕
ff
b7
b7
b0
b0
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
4
1
1
4
3
5
C
Arithmetic Shift Right
↕ –
–
–
↕ ↕ ↕
ff
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
–
–
–
–
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
1B dd
1D dd
1F
dd
MC68HC908AS60 — Rev. 1.0
Technical Data
Central Processor Unit (CPU)
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