Freescale Semiconductor, Inc.
Parallel Input/Output
4.11.1 PPAR — Port pull-up assignment register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
bit 0
Port pull-up assignment (PPAR) $002C HPPUEGPPUEFPPUEBPPUE 0000 1111
0
0
0
0
Bits [7:4] — Not implemented; always read zero
xPPUE — Port x pin pull-up enable
These bits control the on-chip pull-up devices connected to all the
pins on I/O ports B, F, G and H. They are collectively enabled or
disabled via the PAREN bit in the CONFIG register (see below).
1 = Port x pin on-chip pull-up devices enabled.
0 = Port x pin on-chip pull-up devices disabled.
NOTE: Port H [7:4] have pull-up resistors; port H [3:0] have pull-down resistors.
All eight internal resistors are enabled if HPPUE is set.
NOTE: FPPUE and BPPUE have no effect in expanded mode since ports F and
B are dedicated address bus outputs.
4.12 System configuration
One bit in each of the following registers is directly concerned with the
configuration of the I/O ports. For full details on the other bits in the
registers, refer to the appropriate section.
4.12.1 OPT2 — System configuration options register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
System config. options 2 (OPT2) $0038 LIRDV CWOMSTRCHIRVNE LSBF SPR2
0
0
000x 0000
LIRDV — LIR driven (refer to Operating Modes and On-Chip Memory)
1 = Enable LIR drive high pulse.
0 = LIR only driven low – requires pull-up on pin.
Technical Data
MC68HC11P2 — Rev 1.0
Parallel Input/Output
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