Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
5.10.2.4 S3SR2 — SCI3 status register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCI/MI 3 status 2 (S3SR2)
$005D RAF3 0000 0000
0
0
0
0
0
0
0
In S3SR2 only bit 0 is used, to indicate receiver active (see SCSR2 —
SCI status register 2 for details). The other seven bits always read zero.
5.10.2.5 S3DRH, S3DRL — SCI3 data high/low registers
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
$005E R8C T8C
SCI/MI 3 data high (S3DRH)
SCI/MI 3 data low (S3DRL)
0
0
0
0
0
0
undefined
$005F R7T7C R6T6C R5T5C R4T4C R3T3C R2T2C R1T1C R0T0C undefined
S3DRH/S3DRL is a parallel register that performs two functions. It is the
receive data register when it is read, and the transmit data register when
it is written. Reads access the receive data buffer and writes access the
transmit data buffer. Data received or transmitted is double buffered.
See SCDRH, SCDRL — SCI data high/low registers for more details.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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