Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
Additional SCI subsystems
5.10.2.1 S3CR1 — SCI3 control register 1
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCI/MI 3 control 1 (S3CR1)
$005A LOPS3WOMS3 MIE3
M3 WAKE3 ILT3 PE3
PT3 0000 0000
The S3CR1 register provides the control bits that determine word length
and select the method used for the wakeup feature. Bit 5 has an MI BUS
control function detailed below (for details of the other bits see SCCR1
— SCI control register 1).
MIE3 — Motorola Interface Bus Enable 3
1 = MI BUS is enabled for this subsystem.
0 = The SCI functions normally.
When MIE3 is set, the SCI3 registers, bits and pins assume the
functionality required for MI BUS.
5.10.2.2 S3CR2 — SCI3 control register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCI/MI 3 control 2 (S3CR2)
$005B TIE3 TCIE3 RIE3 ILIE3 TE3 RE3 RWU3 SBK3 0000 0000
The S3CR2 register provides the control bits that enable or disable
individual SCI functions. For details of the bits, see SCCR2 — SCI
control register 2.
5.10.2.3 S3SR1 — SCI3 status register 1
State
on reset
PF3 1100 0000
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCI/MI 3 status 1 (S3SR1)
$005C TDRE3 TC3 RDRF3 IDLE3 OR3 NF3
FE3
The bits in S3SR1 indicate certain conditions in the SCI hardware and
are automatically cleared by special acknowledge sequences. For
details of the bits, see SCSR1 — SCI status register 1.
MC68HC11P2 — Rev 1.0
Technical Data
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
