Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
5.10.1.4 S2SR1 — SCI2 status register 1
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
$0054 TDRE2 TC2 RDRF2 IDLE2 OR2 NF2 FE2
SCI/MI 2 status 1 (S2SR1)
PF2 1100 0000
The bits in S2SR1 indicate certain conditions in the SCI hardware and
are automatically cleared by special acknowledge sequences. For
details of the bits, see SCSR1 — SCI status register 1.
5.10.1.5 S2SR2 — SCI2 status register 2
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
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bit 0
SCI/MI 2 status 2 (S2SR2)
0
0
0
0
0
0
0
RAF2 0000 0000
In the S2SR2 only bit 0 is used, to indicate receiver active (see SCSR2
— SCI status register 2). The other seven bits always read zero.
5.10.1.6 S2DRH, S2DRL — SCI2 data high/low registers
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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SCI/MI 2 data high (S2DRH)
SCI/MI 2 data low (S2DRL)
0
0
0
0
0
0
undefined
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undefined
S2DRH/S2DRL is a parallel register that performs two functions. It is the
receive data register when it is read, and the transmit data register when
it is written. Reads access the receive data buffer and writes access the
transmit data buffer. Data received or transmitted is double buffered.
See SCDRH, SCDRL — SCI data high/low registers for more details.
5.10.2 SCI3
SCI3 shares I/O with two of port H’s pins: receive pin RXD3/PH4 and
transmit pin TXD3/PD5. The SCI receive and transmit functions are
enabled by RE and TE respectively, in S3CR2.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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