Mechanical Data and Ordering Information
NOTE: This is the top view of the device.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
B
C
D
E
F
MODCK2 TEXP EXTCLK MODCK1 OP0
ALEA
AS
IPB0
BURST
IRQ2
IRQ6
BB
BR
TEA
BI
CS0
CS3
CS5
N/C
RSTCONF
IPA7
SRESET BADDR29 OP1
WAITA PORESET XTAL
ALEB
TS
TA
BDIP
CS2
CE1A GPLAB3 GPLA0
IPA2
IPA5
D30
IPA4
D31
D29
EXTAL BADDR30 IPB1
BG
GPLA4 GPLA5
WR
CS4
OE
CE2A
GPLAB2
BSA0
CS7
WE0
BSA3
WE2
BSA1
TSIZ0
WE1
BSA2
A31
IPA3 VSSSYN VDDSYN HRESET BADDR28 IRQ4
IRQ3
VDDL
CS1
GPLB4
CS6
VDDL
VDDH
IPA6
IPA1 VSSSYN1
G
H
J
VDDH
VDDH
D28
D7
CLKOUT
D24
D26
D25
D21
IPA0
WE3
TSIZ1
A28
A26
A30
A21
A22
A25
A20
A18
A24
A29
VDDL
GND
VDDH
VDDL
D22
D18
D6
D19
D20
A23
GND
K
L
GND
VDDL
VDDH
D5
D3
D15
D2
D16
D27
D14 VDDL
A14
A10
A19
A12
A27
A15
A17
A16
GND
VDDH
D0
VDDH
M
N
P
R
VDDH
VDDH
A2
A8
A6
A3
A11
A7
A13
A9
D11
D10
D23
D9
D1
D12
D13
PE18
IRQ7
IRQ1
IRQ0
PA2
PA0
MII_MDIO
PB27
VDDL
PC6
VDDL
PE14
PB26
PC11
A1
D17
PE22
PA4
PE31
PA6
PA7
TDO
TCK
PA15
A5
A4
D4
D8
PE25
PA1
PA3
PE19
PE27
PE28
PE30
PA11 MII_COL
PA10
PB28
PC15
A0
PB29
T
PD8
PE26
N/C
PB31
PE15
PE29
PE17
PE24
PE21
PC7
PB19
PB24
PB23
TDI
TMS
PC12
GND
N/C
PB30
N/C
U
PE20
PE23 MII-TX-EN PE16
PC13 MII-CRS PC10
PB25
PA14
TRST
Figure 68. Pinout of the PBGA Package—JEDEC Standard
Table 36 contains a list of the MPC875/870 input and output signals and shows multiplexing and pin assignments.
Table 36. Pin Assignments—JEDEC Standard
Name
Pin Number
Type
Bidirectional
A[0:31]
R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16,
L15, M17, K14, L16, L17, K17, G17, K15, J16, J15, G16, J14, H17, Three-state (3.3 V only)
H16, G15, K16, H14, J17, H15, F17
TSIZ0
REG
F16
Bidirectional
Three-state (3.3 V only)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
72
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
