FEC Electrical Characteristics
15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 34 provides information on the MII serial management channel signal timing. The FEC functions correctly
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 34. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay)
M12 MII_MDIO (input) to MII_MDC rising edge setup
M13 MII_MDIO (input) to MII_MDC rising edge hold
M14 MII_MDC pulse width high
—
10
25
—
ns
ns
0
—
ns
40%
40%
60%
60%
MII_MDC period
MII_MDC period
M15 MII_MDC pulse width low
Figure 67 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
M10
MII_MDIO (output)
M11
MII_MDIO (input)
M12
M13
Figure 67. MII Serial Management Channel Timing Diagram
MPC875/MPC870 Hardware Specifications, Rev. 3.0
70
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
