FEC Electrical Characteristics
Table 32. MII Transmit Signal Timing (continued)
Num
Characteristic
Min
Max
Unit
M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup
MII
4
—
ns
M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
2
—
ns
MII
edge
Figure 65 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (input)
M5
M8
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 65. MII Transmit Signal Timing Diagram
15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 33 provides information on the MII async inputs signal timing.
Table 33. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK period
Figure 66 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 66. MII Async Inputs Timing Diagram
MPC875/MPC870 Hardware Specifications, Rev. 3.0
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
69
Freescale Semiconductor
FREESCALE [ Freescale ]
