Host Interface (HI32)
Table 1-11. Host Interface (Continued)
State During
Signal Name
Type
Signal Description
Reset
HCLK
Input
Input
Host Clock
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Bus Clock input.
Non-PCI bus
When HI32 is programmed to interface a universal non-PCI bus and the HI
function is selected, this signal must be connected to a pull-up resistor or
directly to V
.
CC
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
HAD[16–31]
HD[8–23]
Input/Output
Input/Output
Tri-stated
Host Address/Data 16–31
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 16–31 of the Address/Data bus.
Host Data 8–23
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, these signals are lines 8–23 of the Data bus.
Port B
When the HI32 is configured as GPIO through the DCTR, these signals are
internally disconnected.
These inputs are 5 V tolerant.
HRST
HRST
Input
Input
Tri-stated
Hardware Reset
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Hardware Reset input.
Hardware Reset
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Hardware Reset Schmitt-trigger signal.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
HINTA
Output, open
drain
Tri-stated
Host Interrupt A
When the HI function is selected, this signal is the Interrupt A open-drain
output.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
PVCL
Input
Input
PCI Voltage Clamp
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected and the PCI bus uses a 3 V signal environment, connect this pin to
V
(3.3 V) to enable the high voltage clamping required by the PCI
CC
specifications. In all other cases, including a 5 V PCI signal environment, leave
the input unconnected.
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-15
FREESCALE [ Freescale ]
