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DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ Freescale ]
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Signals/Connections  
Signal Name  
Table 1-11. Host Interface (Continued)  
State During  
Type  
Signal Description  
Reset  
HSERR  
HIRQ  
Output, open  
drain  
Tri-stated  
Host System Error  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host System Error signal.  
Output, open  
drain  
Host Interrupt Request  
When HI32 is programmed to interface with a universal, non-PCI bus and the  
HI function is selected, this is the Host Interrupt Request signal.  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
HSTOP  
Input/  
Tri-stated  
Host Stop  
Output  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host Stop signal.  
HWR/HRW  
Input  
Host Write/Host Read-Write  
When HI32 is programmed to interface with a universal, non-PCI bus and the  
HI function is selected, this is the Host Write/Host Read-Write Schmitt-trigger  
signal.  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
HIDSEL  
Input  
Input  
Input  
Host Initialization Device Select  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host Initialization Device Select signal.  
HRD/HDS  
Host Read/Host Data Strobe  
When HI32 is programmed to interface with a universal, non-PCI bus and the  
HI function is selected, this is the Host Data Read/Host Data Strobe Schmitt-  
trigger signal.  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
HFRAME  
Input/  
Tri-stated  
Host Frame  
Output  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host cycle Frame signal.  
Non-PCI bus  
When HI32 is programmed to interface with a universal, non-PCI bus and the  
HI function is selected, this signal must be connected to a pull-up resistor or  
directly to V  
.
CC  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
DSP56301 Technical Data, Rev. 10  
1-14  
Freescale Semiconductor  
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