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DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ Freescale ]
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M_BME EQU 12  
M_BRE EQU 13  
M_BSTR EQU 14  
; Mastership Enable  
; Refresh Enable  
; Software Triggered Refresh  
M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)  
M_BRP EQU 23 ; Refresh prescaler  
;
Address Attribute Registers  
M_BAT EQU $3  
M_BAAP EQU 2  
M_BPEN EQU 3  
M_BXEN EQU 4  
M_BYEN EQU 5  
M_BAM EQU 6  
; External Access Type and Pin Definition Bits Mask (BAT0-BAT1)  
; Address Attribute Pin Polarity  
; Program Space Enable  
; X Data Space Enable  
; Y Data Space Enable  
; Address Muxing  
M_BPAC EQU 7 ; Packing Enable  
M_BNC EQU $F00  
; Number of Address Bits to Compare Mask (BNC0-BNC3)  
M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)  
;
control and status bits in SR  
M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR  
M_CA EQU 0  
M_V EQU 1  
; Carry  
; Overflow  
M_Z EQU 2  
; Zero  
M_N EQU 3  
; Negative  
M_U EQU 4  
; Unnormalized  
M_E EQU 5  
; Extension  
M_L EQU 6  
; Limit  
M_S EQU 7  
; Scaling Bit  
M_I0 EQU 8  
M_I1 EQU 9  
M_S0 EQU 10  
M_S1 EQU 11  
M_SC EQU 13  
M_DM EQU 14  
M_LF EQU 15  
M_FV EQU 16  
M_SA EQU 17  
M_CE EQU 19  
M_SM EQU 20  
M_RM EQU 21  
M_CP0 EQU22  
M_CP1 EQU 23  
; Interupt Mask Bit 0  
; Interupt Mask Bit 1  
; Scaling Mode Bit 0  
; Scaling Mode Bit 1  
; Sixteen_Bit Compatibility  
; Double Precision Multiply  
; DO-Loop Flag  
; DO-Forever Flag  
; Sixteen-Bit Arithmetic  
; Instruction Cache Enable  
; Arithmetic Saturation  
; Rounding Mode  
; bit 0 of priority bits in SR  
; bit 1 of priority bits in SR  
;
control and status bits in OMR  
M_CDP EQU$300 ; mask for CORE-DMA priority bits in OMR  
M_MA EQU 0  
; Operating Mode A  
M_MB EQU 1  
; Operating Mode B  
M_MC EQU 2  
; Operating Mode C  
M_MD EQU 3  
; Operating Mode D  
M_EBD EQU 4  
M_SD EQU 6  
; External Bus Disable bit in OMR  
; Stop Delay  
M_CDP0 EQU 8  
M_CDP1 EQU 9  
M_BEN EQU 10  
M_TAS EQU 11  
M_BRT EQU 12  
M_XYS EQU 16  
M_EUN EQU 17  
M_EOV EQU 18  
; bit 0 of priority bits in OMR  
; bit 1 of priority bits in OMR  
; Burst Enable  
; TA Synchronize Select  
; Bus Release Timing  
; Stack Extension space select bit in OMR.  
; Extensed stack UNderflow flag in OMR.  
; Extended stack OVerflow flag in OMR.  
DSP56301 Technical Data, Rev. 10  
Freescale Semiconductor  
A-15  
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