Power Consumption Benchmark
M_TC EQU $F0
M_INV EQU 8
M_TRM EQU 9
M_DIR EQU 11
M_DI EQU 12
M_DO EQU 13
; Timer Control Mask (TC0-TC3)
; Inverter Bit
; Timer Restart Mode
; Direction Bit
; Data Input
; Data Output
M_PCE EQU 15 ; Prescaled Clock Enable
M_TOF EQU 20
M_TCF EQU 21
; Timer Overflow Flag
; Timer Compare Flag
;
Timer Prescaler Register Bit Flags
M_PS EQU $600000 ; Prescaler Source Mask
M_PS0 EQU 21
M_PS1 EQU 22
;
Timer Control Bits
M_TC0 EQU 4
M_TC1 EQU 5
M_TC2 EQU 6
M_TC3 EQU 7
; Timer Control 0
; Timer Control 1
; Timer Control 2
; Timer Control 3
;------------------------------------------------------------------------
;
;
;
EQUATES for Direct Memory Access (DMA)
;------------------------------------------------------------------------
;
Register Addresses Of DMA
M_DSTR EQU $FFFFF4; DMA Status Register
M_DOR0 EQU $FFFFF3; DMA Offset Register 0
M_DOR1 EQU $FFFFF2; DMA Offset Register 1
M_DOR2 EQU $FFFFF1; DMA Offset Register 2
M_DOR3 EQU $FFFFF0; DMA Offset Register 3
;
Register Addresses Of DMA0
M_DSR0 EQU $FFFFEF; DMA0 Source Address Register
M_DDR0 EQU $FFFFEE; DMA0 Destination Address Register
M_DCO0 EQU $FFFFED; DMA0 Counter
M_DCR0 EQU $FFFFEC; DMA0 Control Register
;
Register Addresses Of DMA1
M_DSR1 EQU $FFFFEB; DMA1 Source Address Register
M_DDR1 EQU $FFFFEA; DMA1 Destination Address Register
M_DCO1 EQU $FFFFE9; DMA1 Counter
M_DCR1 EQU $FFFFE8; DMA1 Control Register
;
Register Addresses Of DMA2
M_DSR2 EQU $FFFFE7; DMA2 Source Address Register
M_DDR2 EQU $FFFFE6; DMA2 Destination Address Register
M_DCO2 EQU $FFFFE5; DMA2 Counter
M_DCR2 EQU $FFFFE4; DMA2 Control Register
;
Register Addresses Of DMA4
DSP56301 Technical Data, Rev. 10
A-12
Freescale Semiconductor
FREESCALE [ Freescale ]
